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single chip 10base-fl transceiver technical data HFBR-4663 general description the HFBR-4663 single chip 10base-fl transceiver is a highly integrated circuit for ieee 802.3 10base-fl transceivers. this product, when used with hps fiber-optic transmitters and receivers (hfbr-14x4 and hfbr-2416), ensures compliance to the 10base-fl standard with a minimum number of external components and board space. the HFBR-4663 offers a standard ieee 802.3 au interface that allows it to be directly connected to industry standard manchester encoder/decoder chips or an aui connector. the fiber-optic led driver offers a current drive output that directly drives the hfbr-14x4 transmitter. the data quantizer section of the hfbr- 4663 is directly compatible with the output of the hfbr-24x6 fiber-optic receiver and is capable of accepting input signals as low as 2 mvp-p with a 55 db dynamic range. the transmitter automatically inserts 1 mhz signal during idle time and removes this signal on reception. low light is continu- ously monitored for both activity as well as power level. five led status indicators monitor error conditions as well as transmis- sions, receptions, and collisions. ? current driven fiber optic led driver for accurate launch power ? single +5 volt supply ? no crystal or clock required ? five network status led outputs ? available in 28 pin pcc package ? semi-standard option available features ? single chip solution for 10base-fl internal or external medium attachment units (maus) ? specifically designed for use with hfbr-14x4 and hfbr- 24x6 fiber-optic transmitters and receivers ? incorporates an au interface ? highly stable data quantizer with 55 db input dynamic range ? input sensitivity as low as 2 mv p-p caution: the small junction sizes inherent to the design of this component increase the component's suscepti- bility to damage from electrostatic discharge (esd). it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd.
2 block diagram c timer 1 mhz idle signal fiber optic led driver aui receiver txout led drivers jabber gnd col- sqen/jabd tx squelch sqe receive squelch link detect v ref col+ tx rx v thadj loopback mux gnd aui driver aui driver 10 mhz gated oscillator v in + v dc v ref av cc v cc (+5 v) tx+ rx+ +5 v rrset jab lbdis agnd rtset bias +5 v tx- rx- cmp amp v in - xmt rcv clsn lmon v cc tx (+5 v)
3 pin connection pin description pin name function 1 clsn indicates that a collision is taking place. active low led driver, open collector. event is extended with internal timer for visibility. 2 col+ gated 10 mhz oscillation used to indicate a collision, sqe test, or jabber. 3 col- balanced differential line driver outputs that meet aui specifications. 4c timer a capacitor from this pin to v cc determines the link monitor response time. 5 sqen/jabd sqe test enable, jabber disable. when tied low, sqe test is disabled, when tied high sqe test is enabled. when tied to 2.0 v both sqe test and jabber are disabled. 6 rx+ manchester encoded receive data output to the local device. balanced 7 rx- differential line driver outputs that meet aui specifications. 8 lbdis loopback disable. when this pin is tied to v cc , the aui transmit pair data is not looped back to the aui receive pair, and collision is disabled. when this pin is tied to gnd (normal operation) or left floating, the aui transmit pair data is looped back to the aui receiver pair, except during collision. 9v cc +5 v power input. 10 tx+ balanced differential line receiver inputs that meet aui specifications. these 11 tx- inputs may be transformer or capacitively coupled. the tx input pins are internally dc biased for ac coupling. 12 rtset sets the current driven output of the transmitter. 13 rrset a 1% 61.9 k w resistor tied from this pin to v cc sets the biasing currents for internal nodes. 14 lmon link monitor low light led status output. this pin is pulled low when the voltage on the v in +, v in - inputs exceed the minimum threshold set by the v thadj pin, and there are transitions on v in +, v in - indicating an idle signal or active data. if either the voltage on the v in +, v in - inputs fall below the minimum threshold or transitions cease on v in +, v in -, lmon will go high. active low led driver, open collector. sqen/jabd rx+ rx- lbdis v cc tx+ tx- 5 6 7 8 9 10 11 25 24 23 22 21 20 19 v in- agnd v thadj v ref v dc gnd gnd c timer col- col+ clsn jab av cc v in+ rtset rrset lmon xmt rcv v cc tx txout 4321282726 12 13 14 15 16 17 18 top view 28 ?pin pcc q ?28
4 parameter symbol min. max. units storage temperature t s -65 +150 c operating temperature t a 070c lead soldering cycle 260 c temperature lead soldering cycle time 10 sec power supply voltage range v cc -0.3 6.0 v input voltage range digital inputs (sqen, lbdis) -0.3 6.0 v tx+, tx-, v in +, v in - -0.3 6.0 v input current rrset, rtset, jab, clsn, 60 ma xmt, rcv, lmon output current txout 70 ma pin description (cont.) pin name function 1 5 xmt indicates that transmission is taking place. active low led driver, open collector. event is extended with internal timer for visibility. 1 6 rcv indicates that the transceiver is receiving a frame from the optical input. active low led driver, open collector. event is extended with internal timer for visibility. 17 v cc tx +5 v supply for fiber optic led driver. 18 txout fiber optic led driver output. 19 gnd ground reference. 20 gnd ground reference. 21 v dc an external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. if the dc feedback loop is not being used, this pin should be connected to v ref . 22 v ref a 2.5 v reference with respect to gnd. 23 v thadj this input pin sets the link monitor threshold. 24 agnd analog filtered ground. 25 v in - this input pin should be capacitively coupled to the input source or to filtered av cc . (the input resistance is approximately 1.3 k w .) 26 v in + this input pin should be capacitively coupled to the input source or to filtered av cc . (the input resistance is approximately 1.3 k w .) 27 av cc analog filtered +5 v. 28 jab jabber network status led. when in the jabber state, this pin will be low and the transmitter will be disabled. in the jabber ok state this pin will be high. active low led, open collector. absolute maximum ratings [1]
5 electrical characteristics unless otherwise specified, t a = 0 c to 70 c, v cc = v cc tx = 5 v 5% [2,3] parameter condition min. typ. max. units power supply current i cc :v cc = 5 v, rtset = 140 w [4] 220 ma while transmitting led drivers: v cc i ol = 10 ma [5] 0.8 v transmit peak output current [6] rtset = 140 w 47 52 57 ma transmit squelch voltage level -300 -250 -200 mv (tx+, tx-) differential output voltage 550 1200 mv (rx , col ) common mode output voltage 4.0 v (rx , col ) differential output voltage 40 mv imbalance (rx , col ) sqe/jabd sqe test disable 0.3 v both disabled 1.5 v cc - 2 v both enabled v cc - 0.5 v lbdis threshold disabled v cc - 0.1 v enabled 1 v common mode voltage (tx+, tx-) 3.5 v common mode voltage (v in +, v in -) 1.65 v reference voltage 2.35 2.45 2.55 v v ref output source current 5 ma amplifier gain 100 v/v input signal range 2 1600 mv p-p external voltage at v thadj to 0.5 2.7 v set v th input offset v dc = v ref (dc loop active) 3 mv input referred noise 50 mhz bw 25 m v input resistance v in +, v in - 0.8 1.3 2.0 k w input bias current of v thadj -200 10 +200 m a input threshold voltage v thadj = v ref [7] 567mv p-p hysteresis 20 % operating conditions parameter min. typ. max. units supply voltage (v cc ) 4.75 5.0 5.25 v led on current 10 ma rrset 61.9 k 1% w rtset 140 1% w
6 ac electrical characteristics symbol parameter min. typ. max. units transmit t txnpw transmit turn-on pulse width 20 ns t txfpw transmit turn-off pulse width from data to idle 400 2100 ns t txlp transmit loopback start-up delay 500 ns t txody transmit turn-on delay 100 ns t txidf transmit idle frequency 0.85 1.25 mhz t txdc transmit idle duty cycle 45 55 % t txsdy transmit steady state propagation delay 15 50 ns t txj transmit jitter into 31 w load 1.5 ns receive t rxsft receive squelch frequency threshold 2.51 4.5 mhz t rxody receive turn-on delay 270 ns t rxfx last bit received to slow decay output 230 300 ns t rxsdy receive steady state propagation delay 15 50 ns t rxj receive jitter 1.5 ns t ar differential output rise time 20% to 80% (rx , col )4ns t af differential output fall time 20% to 80% (rx , col )4ns collision t cpsqe collision present to sqe assert 0 350 ns t sqexr time for sqe to deactivate after collision 0 700 ns t clf collision frequency 8.5 11.5 mhz t clpdc collision pulse duty cycle 40 50 60 % t sqedy sqe test delay (tx inactive to sqe) 0.6 1.6 m s t sqetd sqe test duration 0.5 1.0 1.5 m s jabber and led timing t jad jabber activation delay 20 70 150 ms `t jrt jabber reset unjab time 250 450 750 ms t jsqe delay from outputs disabled to collision oscillator on 100 ns t led rcv, clsn, xmt on time 8 16 32 ms t llph low light present to lmon high 3 5 10 m s t llcl low light present to lmon low 250 750 ms notes: 1. absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. all voltages unless otherwise specified are measured with respect to ground. 2. limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 3. low duty cycle pulse testing is performed at t a . 4. this does not include the current from the aui pull-down resistors, or led status otuputs. 5. led drivers can sink up to 20 ma, but v ol will be higher. 6. does not include pre-bias current for fiber optic led which would typically be 3 ma. 7. threshold for switching from link fail ot link pass (low light).
7 l3 4.7 m h c2 0.01 u1 hfbr-24x6 8 6 5 2 1 37 4 txout txv cc lbdis c timer vdc vin+ vin? vref vthadj mon jab clsn rcv col r2 360 w r3 360 w r4 39 w r5 39 w r6 360 w r7 360 w c13 0.1 xmt v cc gnd gnd ?rf +vrf rrset rtset col+ tx tx+ rx rx+ sqe 12 13 27 24 20 19 9 ?rf +vrf vin vgnd on sgnd fb out l2 4.7 m h 2 6 7 3 18 17 8 4 21 26 25 22 23 +vrf ?rf ?rf +vrf v cc 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 d2 hlmp-1790 d3 hlmp-1790 d4 hlmp-1700 d5 hlmp-1719 d6 hlmp-1790 d7 hlmp-1700 r15 1.5 k w r16 1.5 k w r17 1.5 k w r18 1.5 k w r19 1.5 k w r20 1.5 k w c11 0.1 c12 0.1 1 r14 1k w 1 1 8 1 u3 54 hfbr-14x4 c4 0.047 c5 0.1 r12 0 r13 00 c3 0.01 r1 10 w c1 0.1 ?rf r8 100 w ?% r9 61.9 k w ?% c10 0.1 1 1 1 1 8 7 10 9 r10 3 k w r11 5 k w 5 4 13 12 2 1 16 15 u4 pe65728 c6 22 10 3 12 6 5 4 d1 1n5817 c7 470 ?0% c8 10 ?0% c9 0.1 l1 470 m h db 15 u12 (+12 volts from aui connector) v cc c11 must be physically close to u3 notes: 1. all resistors ?% unless otherwise shown. 2. all capacitors ?0% unless otherwise shown. 3. the HFBR-4663 data sheet (publication #5091-7391e 4/93) contains errors that have subsequently been corrected in this schematic. 4. all capacitors are in m f. 14 28 1 16 15 3 2 11 10 7 6 5 u5 HFBR-4663 u2 lm2574 + + + figure 1. HFBR-4663 schematic diagram.
8 system description figure 1 shows a schematic diagram of the HFBR-4663 in an internal or external 10base-fl mau. on one side of the transceiver is the au interface and the other is the fiber optic interface. the au interface is ac coupled when used in an external transceiver or an internal transceiver. the au interface for an external transceiver includes isolation transformers, some biasing resistors, and a voltage regulator for power. the fiber optic side of the transceiver requires an external fiber optic transmitter and fiber optic receiver. the transmitter uses a current driven output that directly drives the fiber optic transmitter. the receive side of the transceiver accepts the data after passing through a fiber optic receiver, which consists of a module containing a pin diode and a transimpedance amplifier. au interface the au interface consists of 3 pairs of signals, do, ci and di as shown in figure 1. the do pair contains transmit data from the dte which is received by the transceiver and sent out onto the fiber optic cable. the di pair contains valid data that has been either received from the fiber optic cable or looped back from the do and output through the di pair to the dte. the ci pair indicates whether a collision has occurred. it is an output that oscillates at 10 mhz if a collision, jabber or sqe test has taken place, otherwise it remains idle. when the transceiver is external, these three pairs are ac coupled through isolation transformers, while an internal transceiver may be capacitively coupled. tx+, tx- is internally dc biased (shifted up in voltage) for the proper common mode input voltage. the two 39 w 1% resistors (or one 78 w 1% resistor) tied to he tx+ and tx- pins will provide the proper termination. the ci and di pair, which are output from the transceiver to the aui cable, require 360 w pull down resistors when terminated with a 78 w load. however on a dte card, ci and di do not need 78 w terminating resistors. this also means that the pull down resistors on ci and di can be 1 k w or greater depending upon the particular manchester encoder/ decoder chip used. using higher value pull down resistors as in a dte card will save power. the aui drivers are capable of driving the full 50 meters of cable length and have a rise and fall time of typically 4 ns. in the idle state, the outputs go to the same voltage to prevent dc standing current in the isolation transformers. transmission the transmit function consists of detecting the presence of data from the aui do input (tx+, tx-) and driving that data onto the fiber optic led transmitter. a positive signal on the tx+ lead relative to the tx- lead of the do circuit will result in no current, hence the fiber optic led is in a low light condition. when tx+ is more negative than tx-, the HFBR-4663 will sink current into the chip and the fiber optic led will emit light. before data will be transmitted onto the fiber optic cable from the au interface, it must exceed the squelch requirements for the do pair. the tx squelch circuit serves the function of preventing any noise from being transmitted onto the fiber. this circuit rejects signals with pulse widths less than typically 20 ns (negative going), or with levels less than -250 mv. once tx squelch circuit has unsquelched, it looks for the start of idle signal to turn on the squelch circuit again. the transmitter turns on the squelch again when it receives an input signal at tx+, tx- that is more positive than -250 mv for more than approximately 180 ns. at the start of a packet trans- mission, no more than 2 bits are received from the do circuit and not transmitted onto the fiber optic cable. the difference between start-up delays (bit loss plus steady-state propagation delay) for any two packets that are separated by 9.6 m s or less will not exceed 200 ns. fiber optic led driver the output stage of the trans- mitter is a current mode switch which controls the output light by sinking current through the led into the txout pin. once the current requirement for the led is determined, the rtset resistor is selected. the following equation is used to select the
9 correct rtset resistor: 52 ma rtset= CCCCCC l62 w ( ) iout the transmitter enters the idle state when it detects start of idle on tx+ and tx- input pins. after detecting the start of idle, the transmitter switches to a 1 mhz output idle signal. the output current is switched through the txout pin during the on cycle and the v cc tx pin during the off cycle as shown in figure 2. since the sum of the current in these two pins is constant, v cc tx should be connected as close as possible to the v cc connection for the led. if not driving an optical led directly, a differential output can be generated by tying resistors from v cc tx and txout to v cc as shown in figure 3. the minimum voltage on these two pins should not be less than v cc - 2 v. figure 3. converting optical led driver output to differential ecl. loopback the loopback function emulates a 10base-t transceiver whereby the transmit data sent by the dte is looped back over the aui receive pair. some lan controllers use this loopback information to determine whether a mau is connected by monitoring the carrier sense while transmitting. the software can use this loopback information to determine whether a mau is connected to the dte by checking the status of carrier sense after each packet transmission. when data is received by the chip while transmitting, a collision condition exits. this will cause the collision oscillator to turn on and the data on the di pair will follow v in +, v in -. after a collision is detected, the collision oscillator will remain on until either do or v in +, v in - go idle. loopback can be disabled by strapping lbdis to v cc . in this mode the chip operates as a full duplex transmitter and receiver, and collision detection is disabled. a loopback through the transceiver can be accomplished by tying the fiber transmitter to the receiver. reception the input to the transceiver comes from a fiber optic receiver as shown in figure 1. at the start of packet reception no more than 2.7 bits are received from the fiber cable and not transmitted onto the di circuit. the receive squelch will reject frequencies lower than 2.51 mhz. while in the unsquelch state, the receive squelch circuit looks for the start of idle signal at the end of the packet. start of idle occurs when the input signal remains idle for more than 160 ns. when start of idle is detected, the receive squelch circuit returns to the squelch state and the start of idle signal is output on the di circuit (rx+, rx-). collision whenever the receiver and the transmitter are active at the same time the chip will activate the collision output, except when loopback is disabled (lbdis = vcc). the collision output is a differential square wave matching the aui specifications and capable of driving a 78 w load. the frequency of the square wave is 10 mhz 15% with a 60/40 to 40/60 duty cycle. the collision oscillator also is activated during sqe test and jabber. figure 2. fiber optic led driver structure. v cc tx txout i out v cc tx txout v cc 51 w 51 w 51 w ecl rtset = 560 w i out = 15.9 ma
10 sqe test function signal quality error the sqe test function allows the dte to determine whether the collision detect circuitry is functional. after each trans- mission, during the inter packet gap time, the collision oscillator will be activated for typically 1 m s. the sqe test will not be activated if the chip is in the low light state, or the jabber on state. for sqe to operate, the sqen pin must be tied to v cc . this allows the mau to be interfaced to a dte. the sqe test can be disabled by tying the sqen pin to ground, for a repeater interface. jabber function requirements the jabber function prevents a babbling transmitter from bringing down the network. within the transceiver is a jabber timer that starts at the beginning of each transmission and resets at the end of each transmission. if the transmission lasts longer than 20 ms the jabber logic disables the transmitter, and turns on the collision signal col+, col-. when tx+ and tx- finally go idle, a second timer measures 0.5 seconds of idle time before the transmitter is enabled and collision is turned off. even though the transmitter is disabled during jabber, the 1 mhz idle signal is still transmitted. led drivers the HFBR-4663 has five led drivers. the led driver pins are active low, and the leds are normally off (except for lmon). the leds are tied to their respective pins through a 500 w resistor to 5 volts. the xmt, rcv and clsn pins have pulse stretchers on them which enable the leds to be visible. when transmission or reception occurs, the led xmt, rcv or clsn status pins will activate low for several milli- seconds. if another transmit, receive or collision condition occurs before the timer expires, the led timer will reset and restart the timing. therefore rapid events will leave the leds continuously on. the jab and lmon leds do not have pulse stretchers on them since their conditions occur long enough for the eye to see. low light condition the lmon led output is used to indicate a low light condition. lmon is activated low when both the receive power exceeds the link monitor threshold and there are transitions on v in +, v in - less than 3 m s apart. if either one of these conditions do not exist, lmon will go high. input amplifier the v in +, v in - input signal is fed into a limiting amplifier with a gain of about 100 and input resistance of 1.3 k w . maximum sensitivity is achieved through the use of a dc restoration feedback loop and ac coupling the input. when ac coupled, the input dc bias voltage is set by an on-chip network at about 1.7 v. these coupling capacitors, in conjunction with the input impedance of the amplifier, establish a high pass filter with 3 db corner frequency, f l , at 1 f l = CCCCCCCC 2 p 1300c since the amplifier has a differ- ential input, two capacitors of equal value are required. if the signal driving the input is single ended, one of the coupling capacitors can be tied to av cc as shown in figure 1. the internal amplifier has a lowpass filter built-in to band limit the input signal which in turn will improve the signal noise ratio. although the input is ac coupled, the offset voltage within the amplifier will be present at the amplifiers output. this is represented by v os in figure 4. in order to reduce this error a dc feedback loop is incorporated. this negative feedback loop nulls the offset voltage, forcing v os to be zero. although the capacitor on v dc is non-critical, the pole it creates can affect the stability of the feedback loop. to avoid stability problems, the value of this capacitor should be at least 10 times larger than the input coupling capacitors. figure 4. v out + v out - v os
11 the comparator is a high-speed differential zero crossing detector that slices and accurately digitizes the receive signal. the output of the comparator is fed in parallel into both the receive squelch circuit and the loopback mux. link detect circuitry and low light the link detect circuit monitors the input signal and determines when the input falls below a preset voltage level. when the input falls below a preset voltage, the HFBR-4663 goes into the low light state. in the low light state the transmitter is disabled, but continues sending the i mhz idle signal, the loopback is disabled, the receiver is disabled and the lmon led pin goes to high shutting off the lmon led. to return to the link pass state, the optical receiver power must be 20% higher than the shut-off state. this built-in hysteresis adds stability to the link monitor circuit. once the receiver power threshold is exceeded, the hfbr- 4663 waits 250 ms to 750 ms, then checks to see that tx+, tx- is idle and no data is being received before re-enabling the transmitter, receiver, loopback circuit, and lighting up the lmon led. the v thadj pin is used to adjust the sensitivity of the receiver. the HFBR-4663 is capable of exceeding the 10base-fl specifications for sensitivity. the sensitivity is dependent on the layout of the pc board. a good low noise layout will exceed the 10base-fl specifications, while a poor layout will fail to meet the sensitivity and ber spec. state the link can be switched on if the input exceeds the set threshold for a time given by: c timer x 0.7 v t= CCCCCCCCCCCC 700 m a to switch the link from on to off, the above time will be doubled. a value of 0.05 m f will meet the 10base-fl specifications. differences between 10base-fl and foirl 10base-fl is an improved version of the original foirl standard. the 10base-fl standard allows backward compatibility of a 10base-fl transceiver with a foirl transceiver. the main improve- ments incorporated into 10base- fl are that it can attach to a dte by adding the sqe test, and the distance has been increased from 1 km to 2 km. the other differences are much more subtle. the threshold generator shifts the reference voltage at v thadj through a circuit which has a temperature coefficient matching that of the limiting amplifier. the relationship between the v thadj and the v th (the peak to peak input threshold) is: v thadj = 408 v th (2) in a 10base-fl receiver, there must be less than 1 x 10 -9 bit errors at a receive power level of - 32.5 dbm average. one procedure to determine the sensitivity of a receiver is to start at the lowest optical power level and gradually increase the optical power until the ber is met. in this case the link detect circuit must not disable the receiver (i.e. v thadj should be tied to ground). once the sensitivity of the receiver is determined, v thadj can be set just above the power level that meets the ber specification. this way the receiver will shut-off before the ber is exceeded. for 10-base-fl, v thadj can be tied directly to v ref . however if greater sensitivity is required the circuit in figure 5 can be used to adjust the v thadj voltage. even if v ref is tied to v thadj , it is a good idea to layout a board with these two resistors available. this will allow potential future adjustments without board revisions. the response time of the link detect circuit is set by the c timer pin. starting from the link off figure 5. thresh gen ref vref vthadj r1 r2
12 1. sqe test: the foirl standard did not include the option of attaching a fiber transceiver to a dte. adding the sqe test to 10base-fl enables a 10base-fl transceiver to attach to a dte. 2. 0 to at least 2 km distance: the foirl standard specifies a 1 km distance while 10base-fl specifies 2 km. the additional 1 km distance for 10base-fl comes from an increased flux budget for the cable of 3.5 db. this 3.5 db increase came from an increase of 2.5 db sensitivity for the receiver and a 1 db improvement for the transmitter. the following table illustrates the transmit and receive power requirements for the two standards. note: foirl specifies optical power in peak and 10base-fl specifies it in average. subtracting 3 db from peak will give the average. in the table below the foirl specifications were converted from peak to average power. 3. mau state diagrams are different: the state diagrams for 10base-fl are similar to 10base-t, while the state diagrams for foirl are slightly different. the differences are in the aui loopback, and in the link integrity function. aui loopback - in 10base-fl the do to di loopback is always disabled during a collision, and optical receive data is passed through to di. for foirl there are some cases where loopback continues (i.e. do looped to di) during a collision, and others where loopback is disabled during a collision. 10base-fl is identical to 10base-t in this case. please refer to the ieee standards for greater detail. timing foirl 10basefl parameter differences (bit times) (bit times) ord input to input on di steady state prop delay 0.5 2 start-up delay 3.5 5 output on do to otd_output steady state prop delay 0.5 2 start-up delay 3.5 5 collision deassert to sqe deassert minimum 4.5 0 otd - optical transmit data ord - optical receive data di, do, ci - au interface signals transmit/receive average power min. max. conditions foirl transmitter -12 dbm -21 dbm receiver -12 dbm -30 dbm ber < 10 -10 10base-fl transmitter -12 dbm -20 dbm receiver -12 dbm -32.5 dbm ber < 10 -9 link integrity - 10base-fl adds an additional state to the link integrity test function that will not allow an exit from the low light state until both the transmitter and receiver are idle. in foirl, it is possible to exit from the low light state while still receiving data. mau timing differences - the timing differences between 10base-fl and foirl relate to propagation delays, start-up delays, and collision deassert delays. the following table provides the details of these parameters.
13 timing diagrams figure 6. transmit and loopback timing. figure 7. receive timing. figure 8. collision timing. t x+ valid data valid data t txsdy t txfpw t txody t x- txout t txnpw r x+ valid data r x- t txlp v in+ valid data valid data t rxsdy t ar t rxfx t rxody t af v in- r x+ r x- v in+ cs0 valid data t cpsqe v in- col+ col- txout valid data rx+ rx- v in+ valid data v in- txout valid data t cpsqe col+ cs0 col- tx tx rx rx rx
14 figure 9. collision timing. figure 10. collision timing. figure 11. sqe timing. valid data t sqedy txout col- cs0 col+ t sqetd txout cs0 valid data t sqexr v in+ v in- rx+ rx rx- col+ col- rx rx tx tx tx txout cs0 valid data t sqexr v in+ v in- rx+ rxin rx- col+ col- rxin rxin 1 t clf rxin rxin
15 figure 12. jabber timing. figure 13. led timing. valid t jsqe tx+ col- cs0 col+ t jrt tx- t jad valid data data txout t llcl xmt t led t led lmon v in+ txout v in- rcv v in+ v in- t llph
for technical assistance or the location of your nearest hewlett-packard sales office, distributor or representative call: americas/canada: 1-800-235-0312 or 408-654-8675 far east/australasia: call your local hp sales office. japan: (81 3) 3335-8152 europe: call your local hp sales office. data subject to change. copyright ? 1997 hewlett-packard co. obsoletes 5091-7391e (4/93) printed in u.s.a. 5965-8597e (4/97)

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